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| AAT3215 150mA CMOS High Performance LDO General Description The AAT3215 MicroPowerTM Low Dropout Linear Regulator is ideally suited for portable applications where low noise, extended battery life and small size are critical. The AAT3215 has been specifically designed for very low output noise performance, fast transient response and high power supply rejection ratio (PSRR), making it ideal for powering sensitive RF circuits. Other features include low quiescent current, typically 95A, and low dropout voltage which is typically less than 140mV at full output current. The device is output short circuit protected and has a thermal shutdown circuit for additional protection under extreme conditions. The AAT3215 also features a low-power shutdown mode for extended battery life. A reference bypass pin has been provided to improve PSRR performance and output noise, by connecting an external capacitor from the AAT3215's reference output to ground. The AAT3215 is available in a space saving 5-pin SOT-23 or 8-pin SC70-JW package in 8 factory programmed voltages of 2.5V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, 3.3V, or 3.5V. Features * * * * * PowerLinearTM * * * * * * * * * * Low Dropout - 140mV at 150mA Guaranteed 150mA Output High accuracy 1.5% 95A Quiescent Current High Power Supply Ripple Rejection * 70 dB at 1kHz * 50 dB at 10kHz Very low self noise 45Vrms/rtHz Fast line and load transient response Short circuit protection Over-Temperature protection Uses Low ESR ceramic capacitors Noise reduction bypass capacitor Shutdown mode for longer battery life Low temperature coefficient 8 Factory programmed output voltages SOT-23 5-pin or SC70-JW 8-pin package Preliminary Information Applications * * * * * Cellular Phones Notebook Computers Portable Communication Devices Personal Portable Electronics Digital Cameras Typical Application VIN IN OUT VOUT AAT3215 ON/OFF EN GND 1F 10nF 2.2F BYP GND GND 3215.2002.03.0.91 1 AAT3215 150mA CMOS High Performance LDO Pin Descriptions Pin # SOT23-5 SC70JW-8 Symbol IN GND EN Function Input voltage pin - should be decoupled with 1F or greater capacitor. Ground connection pin Enable pin - this pin is internally pulled high. When pulled low the PMOS pass transistor turns off and all internal circuitry enters low-power mode, consuming less than 1A. Bypass capacitor connection - to improve AC ripple rejection, connect a 10nF capacitor to GND. This will also provide a soft start function. Output pin - should be decoupled with 2.2F capacitor. 1 2 3 5, 6 8 7 4 1 BYP 5 2, 3, 4 OUT Pin Configuration SOT-23-5 (Top View) SC70JW-8 (Top View) IN GND EN 15 2 34 OUT BYP BYP OUT OUT OUT 1 2 8 7 3 4 6 5 GND EN IN IN 1 2 2 3215.2002.03.0.91 AAT3215 150mA CMOS High Performance LDO Absolute Maximum Ratings Symbol VIN IOUT TJ TLEAD (TA=25C unless otherwise noted) Value 6 PD/(VIN-VO) -40 to 150 300 Description Input Voltage DC Output Current Operating Junction Temperature Range Maximum Soldering Temperature (at leads, 10 sec) Units V mA C C Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time. Thermal Information Symbol JA PD Description Maximum Thermal Resistance1 (SOT23-5, SC70JW-8) Maximum Power Dissipation1 (SOT23-5, SC70JW-8) Rating 190 526 Units C/W mW Note 1: Mounted on a demo board. Recommended Operating Conditions Symbol VIN T Description Input Voltage Ambient Temperature Range Rating (VOUT+0.3) to 5.5 -40 to +85 Units V C Electrical Characteristics Symbol VOUT IOUT VDO ISC IQ ISD VOUT/VOUT*VIN VOUT(line) VOUT(load) VEN(L) VEN(H) IEN PSRR TSD THYS eN TC (VIN=VOUT(NOM)+1V, IOUT=1mA, COUT=2.2F, CIN=1f, CBYP=10nF, TA= -40 to 85C unless otherwise noted. Typical values are TA=25C) Description Output Voltage Tolerance Output Current Dropout Voltage1 Short Circuit Current Ground Current Shutdown Current Line Regulation Dynamic Line Regulation Dynamic Load Regulation Enable Threshold Low Enable Threshold High Leakage Current on Enable Pin Power Supply Rejection Ratio Conditions IOUT = 1mA to 150mA Min Typ Max TA=25C -1.5 TA=-40 to 85C -2.5 150 140 600 95 1.5 2.5 250 150 1 0.07 1 30 0.6 1.5 1 70 50 47 150 10 45 22 Units % % mA mV mA A A %/V mV mV V V A dB C C Vrms/rtHz ppm/C VOUT > 1.2V IOUT = 150mA VOUT < 0.4V VIN = 5V, No load, EN = VIN VIN = 5V, EN = 0V VIN = VOUT + 1 to 5.5V VIN=VOUT+1V to VOUT+2V, IOUT=150mA, TR/TF =2s IOUT = 1mA to 150mA, TR<5s VEN = 5V IOUT=10mA, CBYP=10nF 1 kHz 10kHz 1MHz Over Temp Shutdown Threshold Over Temp Shutdown Hysteresis Output Noise Noise Power BW = 300Hz-50kHz Output Voltage Temp. Coeff. Note 1: VDO is defined as VIN - VOUT when VOUT is 98% of nominal. 3215.2002.03.0.91 3 AAT3215 150mA CMOS High Performance LDO Typical Characteristics (Unless otherwise noted, VIN = 5V, TA = 25C) Dropout Voltage vs. Temperature 200 3.1 Dropout Characteristics IOUT=10mA IOUT=0mA IOUT=150mA 2.9 Dropout Voltage (mV) 180 160 140 120 100 80 60 40 20 0 -40 -20 IL=150mA 3.0 IL=100mA IL=50mA 2.8 IOUT=100mA IOUT=50mA 2.9 3.0 3.1 3.2 3.3 2.7 0 20 40 60 80 100 120 Temperature (C) Vin Dropout Voltage vs. Output Current 200 120 Ground Current vs. Input Voltage Dropout Voltage (mV) 180 160 140 120 100 80 60 40 20 0 0 50 100 150 VOUT=3.0V 100 IGND (A) 80 60 40 20 0 2 IOUT=0 IOUT=5mA IOUT=150mA 3 4 5 Output Current (mA) VIN Ground Current vs. Temperature VOUT=3.0V 105 100 3.014 3.013 Output Voltage vs. Temperature Output Voltage 0 50 100 150 IGND (A) 3.012 3.011 3.01 3.009 3.008 95 90 85 80 -50 3.007 -50 0 50 100 150 Temperature (C) Temperature (C) 4 3215.2002.03.0.91 AAT3215 150mA CMOS High Performance LDO Typical Characteristics (Unless otherwise noted, VIN = 5V, TA = 25C) On/Off Transient Response No CBYP Capacitor On/Off Transient Response CBYP=10nF EN (2V/div) VOUT (1V/div) 10mA 10mA 150mA EN (2V/div) VOUT (1V/div) 150mA 100s/div 5ms/div Line Transient Response 3.04 3.03 3.02 6 5 4 3.10 3.05 3.00 Load Transient Response 500 400 300 200 100 0 -100 3.01 3.00 2.99 2.98 3 2 1 0 2.95 2.90 2.85 2.80 5s/div 100 s/div Short Circuit Current 1.2 1 0.8 90 80 Power Supply Rejection Ratio vs. Frequency IOUT=150mA COUT=10f 4.7f 2.2f PSRR (dB) Isc(A) 70 60 50 40 30 20 10 0 10 0.6 0.4 0.2 0 1.0f 100 1k 10k 100k 1m 10m 10ms/div Frequency (Hz) 3215.2002.03.0.91 IOUT (mA) VOUT VOUT VIN 5 AAT3215 150mA CMOS High Performance LDO Typical Characteristics (Unless otherwise noted, VIN = 5V, TA = 25C) Output Self Noise Noise Amplitude in nVrms/Hz (50nVrms/Hz per DIV) 500 0 10 100 1k 10k 100k 1m 10m Frequency (Hz) 6 3215.2002.03.0.91 AAT3215 150mA CMOS High Performance LDO Functional Block Diagram IN Over-Current Protection Over-Temperature Protection OUT Error Amplifier EN BYP Voltage Reference GND Functional Description The AAT3215 is intended for LDO regulator applications where output current load requirements range from no load to 150mA. The advanced circuit design of the AAT3215 provides excellent input to output isolation, which allows for good power supply ripple rejection characteristics. To optimize for very low output self noise performance, a bypass capacitor pin has been provided to decrease noise generated by the internal voltage reference. This bypass capacitor will also enhance PSRR behavior. The two combined characteristics of low noise and high PSRR make the AAT3215 a truly high performance LDO regulator especially well suited for circuit applications which are sensitive to their power source. The LDO regulator output has been specifically optimized to function with low cost, low ESR ceramic capacitors. However, the design will allow for operation over a wide range of capacitor types. The device enable circuit is provided to shutdown the LDO regulator for power conservation in portable products. The enable circuit has an additional output capacitor discharge circuit to assure sharp application circuit turn off upon device shutdown. This LDO regulator has complete short circuit and thermal protection. The integral combination of these two internal protection circuits give the AAT3215 a comprehensive safety system during extreme adverse operating conditions. Device power dissipation is limited to the package type and thermal dissipation properties. Refer to the thermal considerations discussion in the section for details on device operation at maximum output current loads. 7 3215.2002.03.0.91 AAT3215 150mA CMOS High Performance LDO Applications Information To assure the maximum possible performance is obtained from the AAT3215, please refer to the following application recommendations. In low output current applications where output load is less then 10mA, the minimum value for COUT can be as low as 0.47F. Bypass Capacitor and Low Noise Applications A bypass capacitor pin is provided to enhance the very low noise characteristics of the AAT3215 LDO regulator. The bypass capacitor is not necessary for operation of the AAT3215. However, for best device performance, a small ceramic capacitor should be placed between the Bypass pin (BYP) and the device ground pin (GND). The value of CBYP may range from 470pF to 10nF. For lowest noise and best possible power supply ripple rejection performance a 10nF capacitor should be used. To practically realize the highest power supply ripple rejection and lowest output noise performance, it is critical that the capacitor connection between the BYP pin and GND pin be direct and PCB traces should be as short as possible. Refer to the PCB Layout Recommendations section of this document for examples. There is a relationship between the bypass capacitor value and the LDO regulator turn on time. In applications where fast device turn on time is desired, the value of CBYP should be reduced. In applications where low noise performance and/ or ripple rejection are less of a concern, the bypass capacitor may be omitted. The fastest device turn on time will be realized when no bypass capacitor is used. DC leakage on this pin can affect the LDO regulator output noise and voltage regulation performance. For this reason, the use of a low leakage, high quality ceramic (NPO or COG type) or film capacitor is highly recommended. Input Capacitor Typically a 1F or larger capacitor is recommended for CIN in most applications. A CIN capacitor is not required for basic LDO regulator operation. However, if the AAT3215 is physically located more than 3 centimeters from an input power source, a CIN capacitor will be needed for stable operation. CIN should be located as close to the device VIN pin as practically possible. CIN values greater than 1F will offer superior input line transient response and will assist in maximizing the highest possible power supply ripple rejection. Ceramic, tantalum or aluminum electrolytic capacitors may be selected for CIN. There is no specific capacitor ESR requirement for CIN. However, for 150mA LDO regulator output operation, ceramic capacitors are recommended for CIN due to their inherent capability over tantalum capacitors to withstand input current surges from low impedance sources such as batteries in portable devices. Output Capacitor For proper load voltage regulation and operational stability, a capacitor is required between pins VOUT and GND. The COUT capacitor connection to the LDO regulator ground pin should be made as direct as practically possible for maximum device performance. The AAT3215 has been specifically designed to function with very low ESR ceramic capacitors. Although the device is intended to operate with these low ESR capacitors, it is stable over a very wide range of capacitor ESR, thus it will also work with higher ESR tantalum or aluminum electrolytic capacitors. However, for best performance, ceramic capacitors are recommended. Typical output capacitor values for maximum output current conditions range from 1F to 10F. Applications utilizing the exceptionally low output noise and optimum power supply ripple rejection characteristics of the AAT3215 should use 2.2F or greater for COUT. If desired, COUT may be increased without limit. Capacitor Characteristics Ceramic composition capacitors are highly recommended over all other types of capacitors for use with the AAT3215. Ceramic capacitors offer many advantages over their tantalum and aluminum electrolytic counterparts. A ceramic capacitor typically has very low ESR, is lower cost, has a smaller PCB footprint and is non-polarized. Line and load transient response of the LDO regulator is improved by using low ESR ceramic capacitors. Since ceramic capacitors are non-polarized, they are not prone to incorrect connection damage. 3215.2002.03.0.91 8 AAT3215 150mA CMOS High Performance LDO Applications Information Equivalent Series Resistance (ESR): ESR is a very important characteristic to consider when selecting a capacitor. ESR is the internal series resistance associated with a capacitor, which includes lead resistance, internal connections, size and area, material composition and ambient temperature. Typically capacitor ESR is measured in milliohms for ceramic capacitors and can range to more than several ohms for tantalum or aluminum electrolytic capacitors. Ceramic Capacitor Materials: Ceramic capacitors less than 0.1F are typically made from NPO or COG materials. NPO and COG materials are typically tight tolerance very stable over temperature. Larger capacitor values are typically composed of X7R, X5R, Z5U and Y5V dielectric materials. Large ceramic capacitors, typically greater then 2.2F are often available in the low cost Y5V and Z5U dielectrics. These two material types are not recommended for use with LDO regulators since the capacitor tolerance can vary more than 50% over the operating temperature range of the device. A 2.2F Y5V capacitor could be reduced to 1F over temperature, this could cause problems for circuit operation. X7R and X5R dielectrics are much more desirable. The temperature tolerance of X7R dielectric is better than 15%. Capacitor area is another contributor to ESR. Capacitors which are physically large in size will have a lower ESR when compared to a smaller sized capacitor of an equivalent material and capacitance value. These larger devices can improve circuit transient response when compared to an equal value capacitor in a smaller package size. Consult capacitor vendor data sheets carefully when selecting capacitors for LDO regulators. When the LDO regulator is in the shutdown mode, an internal 1.5k resistor is connected between VOUT and GND. This is intended to discharge COUT when the LDO regulator is disabled. The internal 1.5k has no adverse effect on device turn on time. Short Circuit Protection The AAT3215 contains an internal short circuit protection circuit that will trigger when the output load current exceeds the internal threshold limit. Under short circuit conditions the output of the LDO regulator will be current limited until the short circuit condition is removed from the output or LDO regulator package power dissipation exceeds the device thermal limit. Thermal Protection The AAT3215 has an internal thermal protection circuit which will turn on when the device die temperature exceeds 150C. The internal thermal protection circuit will actively turn off the LDO regulator output pass device to prevent the possibility of over temperature damage. The LDO regulator output will remain in a shutdown state until the internal die temperature falls back below the 150C trip point. The combination and interaction between the short circuit and thermal protection systems allow the LDO regulator to withstand indefinite short circuit conditions without sustaining permanent damage. No-Load Stability The AAT3215 is designed to maintain output voltage regulation and stability under operational noload conditions. This is an important characteristic for applications where the output current may drop to zero. Reverse Output to Input Voltage Conditions and Protection Under normal operating conditions a parasitic diode exists between the output and input of the LDO regulator. The input voltage should always remain greater then the output load voltage maintaining a reverse bias on the internal parasitic diode. Conditions where VOUT might exceed VIN should be avoided since this would forward bias the internal parasitic diode and allow excessive current flow into the VOUT pin possibly damaging the LDO regulator. Enable Function The AAT3215 features an LDO regulator enable/ disable function. This pin (EN) is active high and is compatible with CMOS logic. To assure the LDO regulator will switch on, the EN turn on control level must be greater than 2.0 volts. The LDO regulator will go into the disable shutdown mode when the voltage on the EN pin falls below 0.6 volts. If the enable function is not needed in a specific application, it may be tied to VIN to keep the LDO regulator in a continuously on state. 3215.2002.03.0.91 9 AAT3215 150mA CMOS High Performance LDO Applications Information In applications where there is a possibility of VOUT exceeding VIN for brief amounts of time during normal operation, the use of a larger value CIN capacitor is highly recommended. A larger value of CIN with respect to COUT will effect a slower CIN decay rate during shutdown, thus preventing VOUT from exceeding VIN. In applications where there is a greater danger of VOUT exceeding VIN for extended periods of time, it is recommended to place a schottky diode across VIN to VOUT (connecting the cathode to VIN and anode to VOUT). The Schottky diode forward voltage should be less than 0.45 volts. pation and the input to output voltage drop across the LDO regulator. Refer to the following simple equation: IOUT(MAX) < PD(MAX) / (VIN - VOUT) For example, if VIN = 5V, VOUT = 3V and TA = 25, IOUT(MAX) < 264mA. If the output load current were to exceed 264mA or if the ambient temperature were to increase, the internal die temperature will increase. If the condition remained constant, the LDO regulator thermal protection circuit will activate. To figure what the maximum input voltage would be for a given load current refer to the following equation. This calculation accounts for the total power dissipation of the LDO Regulator, including that caused by ground current. PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND) This formula can be solved for VIN to determine the maximum input voltage. VIN(MAX) = (PD(MAX) + (VOUT x IOUT)) / (IOUT + IGND) The following is an example for an AAT3215 set for a 2.5 volt output: From the discussion above, PD(MAX) was determined to equal 526mW at TA = 25C. VOUT = 2.5 volts IOUT = 150mA IGND = 150A VIN(MAX)=(526mW+(2.5Vx150mA))/(150mA +150A) VIN(MAX) = 6.00V Thus, the AAT3215 can sustain a constant 2.5V output at a 150mA load current as long as VIN is 6.00V at an ambient temperature of 25C. 6.0V is the absolute maximum voltage where an AAT3215 would never be operated, thus at 25C, the device would not have any thermal concerns or operational VIN(MAX) limits. This situation can be different at 85C. The following is an example for an AAT3215 set for a 2.5 volt output at 85C: From the discussion above, PD(MAX) was determined to equal 211mW at TA = 85C. Thermal Considerations and High Output Current Applications The AAT3215 is designed to deliver a continuous output load current of 150mA under normal operating conditions. The limiting characteristic for the maximum output load current safe operating area is essentially package power dissipation and the internal preset thermal limit of the device. In order to obtain high operating currents, careful device layout and circuit operating conditions need to be taken into account. The following discussions will assume the LDO regulator is mounted on a printed circuit board utilizing the minimum recommended footprint as stated in the layout considerations section of the document. At any given ambient temperature (TA) the maximum package power dissipation can be determined by the following equation: PD(MAX) = [TJ(MAX) - TA] / JA Constants for the AAT3215 are TJ(MAX), the maximum junction temperature for the device which is 125C and JA = 190C/W, the package thermal resistance. Typically, maximum conditions are calculated at the maximum operating temperature where TA = 85C, under normal ambient conditions TA = 25C. Given TA = 85, the maximum package power dissipation is 211mW. At TA = 25C, the maximum package power dissipation is 526mW. The maximum continuous output current for the AAT3215 is a function of the package power dissi- 10 3215.2002.03.0.91 AAT3215 150mA CMOS High Performance LDO Applications Information VOUT = 2.5 volts IOUT = 150mA IGND = 150uA VIN(MAX)=(211mW+(2.5Vx150mA))/(150mA +150uA) VIN(MAX) = 3.90V Higher input to output voltage differentials can be obtained with the AAT3215, while maintaining device functions within the thermal safe operating area. To accomplish this, the device thermal resistance must be reduced by increasing the heat sink area or by operating the LDO regulator in a duty cycled mode. For example, an application requires VIN = 4.2V while VOUT = 2.5V at a 150mA load and TA = 85C. VIN is greater than 3.90V, which is the maximum safe continuous input level for VOUT = 2.5V at 150mA for TA = 85C. To maintain this high input voltage and output current level, the LDO regulator must be operated in a duty cycled mode. Refer to the following calculation for duty cycle operation: PD(MAX) is assumed to be 211mW IGND = 150A IOUT = 150mA VIN = 4.2 volts VOUT = 2.5 volt %DC=100(PD(MAX)/((VIN-VOUT)IOUT+(VINxIGND)) %DC=100(211mW/((4.2V-2.5V)150mA+(4.2Vx150A)) %DC = 85.54% For a 150mA output current and a 2.7volt drop across the AAT3215 at an ambient temperature of 85C, the maximum on time duty cycle for the device would be 85.54%. The following family of curves show the safe operating area for duty cycled operation from ambient room temperature to the maximum operating level. 3.5 Device Duty Cycle vs. V DROP VOUT = 2.5V @ 25 C 3.5 Voltage Drop (V) 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 90 100 200mA Duty Cycle (%) Device Duty Cycle vs. VDROP VOUT= 2.5V @ 50 C 3.5 Voltage Drop (V) 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 90 100 200mA 150mA Duty Cycle (%) Device Duty Cycle vs. VDROP VOUT = 2.5V @ 85 C Voltage Drop (V) 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 100mA 200mA 150mA 90 100 Duty Cycle (%) 3215.2002.03.0.91 11 AAT3215 150mA CMOS High Performance LDO Applications Information High Peak Output Current Applications Some applications require the LDO regulator to operate at continuous nominal level with short duration high current peaks. The duty cycles for both output current levels must be taken into account. To do so, one would first need to calculate the power dissipation at the nominal continuous level, then factor in the additional power dissipation due to the short duration high current peaks. For example, a 2.5V system using a AAT3215IGV2.5-T1 operates at a continuous 100mA load current level and has short 150mA current peaks. The current peak occurs for 378s out of a 4.61ms period. It will be assumed the input voltage is 4.2V. First the current duty cycle in percent must be calculated: % Peak Duty Cycle: X/100 = 378s/4.61ms % Peak Duty Cycle = 8.2% The LDO Regulator will be under the 100mA load for 91.8% of the 4.61ms period and have 150mA peaks occurring for 8.2% of the time. Next, the continuous nominal power dissipation for the 100mA load should be determined then multiplied by the duty cycle to conclude the actual power dissipation over time. PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND) PD(100mA) = (4.2V - 2.5V)100mA + (4.2V x 150A) PD(100mA) = 170.6mW PD(91.8%D/C) = %DC x PD(100mA) PD(91.8%D/C) = 0.918 x 170.6mW PD(91.8%D/C) = 156.6mW The power dissipation for 100mA load occurring for 91.8% of the duty cycle will be 156.6mW. Now the power dissipation for the remaining 8.2% of the duty cycle at the 150mA load can be calculated: PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND) PD(150mA) = (4.2V - 2.5V)150mA + (4.2V x 150mA) PD(150mA) = 255.6mW PD(8.2%D/C) = %DC x PD(150mA) PD(8.2%D/C) = 0.082 x 255.6mW PD(8.2%D/C) = 21mW The power dissipation for 150mA load occurring for 8.2% of the duty cycle will be 21mW. Finally, the 12 two power dissipation levels can summed to determine the total true power dissipation under the varied load. PD(total) = PD(100mA) + PD(150mA) PD(total) = 156.6mW + 21mW PD(total) = 177.6mW The maximum power dissipation for the AAT3215 operating at an ambient temperature of 85C is 211mW. The device in this example will have a total power dissipation of 177.6mW. This is well within the thermal limits for safe operation of the device. Printed Circuit Board Layout Recommendations In order to obtain the maximum performance from the AAT3215 LDO regulator, very careful attention must be considered in regard to the printed circuit board (PCB) layout. If grounding connections are not properly made, power supply ripple rejection, low output self noise and transient response can be compromised. Figure 1 shows a common LDO regulator layout scheme. The LDO Regulator, external capacitors (CIN, COUT and CBYP) and the load circuit are all connected to a common ground plane. This type of layout will work in simple applications where good power supply ripple rejection and low self noise are not a design concern. For high performance applications, this method is not recommended. The problem with the layout in Figure 1 is the bypass capacitor and output capacitor share the same ground path to the LDO regulator ground pin along with the high current return path from the load back to the power supply. The bypass capacitor node is connected directly to the LDO regulator internal reference, making this node very sensitive to noise or ripple. The internal reference output is fed into the error amplifier, thus any noise or ripple from the bypass capacitor will be subsequently amplified by the gain of the error amplifier. This effect can increase noise seen on the LDO regulator output as well as reduce the maximum possible power supply ripple rejection. There is PCB trace impedance between the bypass capacitor connection to ground and the LDO regulator ground connection. When the high load current returns through this path, a small ripple voltage is created, feeding into the CBYP loop. 3215.2002.03.0.91 AAT3215 150mA CMOS High Performance LDO Applications Information VIN IIN ILOAD VIN EN LDO Regulator GND IGND VOUT BYP DC INPUT CIN CBYP IBYP + noise CBYP GND LOOP COUT RLOAD IRIPPLE GND RTRACE RTRACE RTRACE RTRACE ILOAD return + noise and ripple Figure 1: Common LDO Regulator Layout with CBYP Ripple feedback loop Figure 2 shows the preferred method for the bypass and output capacitor connections. For low output noise and highest possible power supply ripple rejection performance, it is critical to connect the IIN bypass and output capacitor directly to the LDO regulator ground pin. This method will eliminate any load noise or ripple current feedback through the LDO regulator. ILOAD VIN VIN EN LDO Regulator GND VOUT BYP DC INPUT CIN IRIPPLE IGND CBYP IBYP only COUT RLOAD GND RTRACE RTRACE RTRACE RTRACE ILOAD return + noise and ripple Figure 2: Recommended LDO Regulator Layout Evaluation Board Layout The AAT3215 evaluation layout follows the recommend printed circuit board layout procedures and can be used as an example for good application layouts. Note: Board layout shown is not to scale. Figure 3: Evaluation board component side layout Figure 4: Evaluation board solder side layout Figure 5: Evaluation board top side silk screen layout / assembly drawing 13 3215.2002.03.0.91 AAT3215 150mA CMOS High Performance LDO Ordering Information Output Voltage 2.5V 2.7V 2.8V 2.85V 2.9V 3.0V 3.3V 3.5V 2.5V 2.7V 2.8V 2.85V 2.9V 3.0V 3.3V 3.5V Package SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-5 SC70JW-8 SC70JW-8 SC70JW-8 SC70JW-8 SC70JW-8 SC70JW-8 SC70JW-8 SC70JW-8 Marking Part Number Bulk N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Tape and Reel AAT3215IGV-2.5-T1 AAT3215IGV-2.7-T1 AAT3215IGV-2.8-T1 AAT3215IGV-2.85-T1 AAT3215IGV-2.9-T1 AAT3215IGV-3.0-T1 AAT3215IGV-3.3-T1 AAT3215IGV-3.5-T1 AAT3215IJS-2.5-T1 AAT3215IJS-2.7-T1 AAT3215IJS-2.8-T1 AAT3215IJS-2.85-T1 AAT3215IJS-2.9-T1 AAT3215IJS-3.0-T1 AAT3215IJS-3.3-T1 AAT3215IJS-3.5-T1 14 3215.2002.03.0.91 AAT3215 150mA CMOS High Performance LDO Package Information SOT-23-5 e S1 Dim A A1 A2 b c D E e H L S S1 E H D A2 A1 A c S b L Millimeters Min Max 1.00 1.30 0.00 0.10 0.70 0.90 0.35 0.50 0.10 0.25 2.70 3.10 1.40 1.80 1.90 2.60 3.00 0.37 0.45 0.55 0.85 1.05 1 9 Inches Min Max 0.039 0.051 0.000 0.004 0.028 0.035 0.014 0.020 0.004 0.010 0.106 0.122 0.055 0.071 0.075 0.102 0.118 0.015 0.018 0.022 0.033 0.041 1 9 SC70JW-8 e e e Dim E E1 L A A1 A2 D e b c 1 E b D 0.048REF c A2 A Millimeters Min Max 2.10 BSC 1.75 2.00 0.23 0.40 1.10 0 0.10 0.70 1.00 2.00 BSC 0.50 BSC 0.15 0.30 0.10 0.20 0 8 4 10 Inches Min Max 0.083 BSC 0.069 0.079 0.009 0.016 0.043 0.004 0.028 0.039 0.079 BSC 0.020 BSC 0.006 0.012 0.004 0.008 0 8 4 10 A1 1 L E1 3215.2002.03.0.91 15 AAT3215 150mA CMOS High Performance LDO This page intentionally left blank. Advanced Analogic Technologies, Inc. 1250 Oakmead Parkway, Suite 310, Sunnyvale, CA 94086 Phone (408) 524-9684 Fax (408) 524-9689 16 3215.2001.11.0.9 |
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